This invention relates to data processing systems and more specifically is concerned with arrangements for monitoring the operation of such systems.
One known method of monitoring a data processing system is by using parity checking to detect failures in individual circuits such as registers. Checking may be carried out in each of a number of separate modules and the results of the individual checks may be combined in a central monitoring unit.
One limitation of known checking arrangements is that they are not normally capable of detecting failure of the clock signal supply to a module. If the clock signal fails while the contents of the registers in the module are all correct, the registers remain in this correct state and hence the check continues to indicate correct operation. One object of the invention is to overcome this limitation.
Another problem which arises in known checking arrangements is that the failure signal produced by a checking circuit may itself fail, and this may result in a false indication that the module is operating correctly.